Partner:
BME
Advanced Technology:
Reliability testing capabilities
Contact:
Marta Rencz
Gusztav Hantos
Email:
hantos@eet.bme.hu
Versatile Reliability Tester
The reliability test environment integrates a set of appropriate hardware and software components built around the de facto industry standard T3Ster equipment of Mentor Graphics. This versatile system monitors the electric, thermal and even optical parameters of the device under test during freely customizable test sequences.
The core of the system is the Main Control Box (1). It is responsible for the control of the external hardware components, for the signal conditionings of the DUTs and for the measurement data storage. In the actual configuration (as shown on Figure 1) a Mentor Graphics T3Ster transient tester (2), an Agilent N5770A power supply unit (3), a Mentor Graphics HV10V100 power booster (4), a Julabo F25-MC refrigerated/heating circulator (8) and a Weiss WK3-340/70 climate chamber (9) are connected externally. The DUTs (6) are mounted onto a coldplate (7) in the displayed setup. Between the DUTs and the coldplate, special sample holders can be mounted for further measurement system attachment. The user interface (5) and control of certain (less critical) processes are served by the embedded PC of the Main Control Box.
The system was designed for flexible operation in long term power, temperature or relative humidity cycling conditions beyond static storage tests. The operation of the test system is independent of the physical nature of the sample sets and it is possible to define different timing and powering schemes during an active cycling.
Typical use cases
Such a reliability tester was developed to serve as a low and medium power laboratory test environment, ideal to carry out final reliability tests on up from component level (RF modules, sensors, PSUs, drivers, LEDs, FETs) to project demonstrators. Typical use cases range from functional tests and real application environment simulations on IoT and CPS based devices, to thermally and moisture induced package and silicon level failure mode monitoring during lifetime tests.
Further information can be found at
Guidelines for elaborating customized reliability tests:
- Environmental and endurance test methods for semiconductor devices
https://home.jeita.or.jp/tsc/std-pdf/ED-4701_100.pdf - G. Hantos, J. Hegedüs, M. Rencz and A. Poppe, “Aging tendencies of power MOSFETs — A reliability testing method combined with thermal performance monitoring,” 2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Budapest, 2016, pp. 220-223.
https://doi.org/10.1109/THERMINIC.2016.7749055
Further contacts
Janos Hegedus hegedus@eet.bme.hu